1. Field of the Invention
The present invention relates to semiconductor devices and methods for fabricating semiconductor devices. More particularly, the invention relates to flash memory devices and methods for fabricating the same.
2. Description of the Related Art
A cell array of a memory device may include a plurality of cell transistors. In flash memory devices, a channel impurity concentration of the cell transistors constituting a cell array is, in general, closely related to a threshold voltage, a leakage current and/or a boosting efficiency. Accordingly, it is desired to provide cell transistors, which are employable by memory devices, and which have reduced current leakage characteristics, reduced dispersion of channel impurity concentration and an appropriate impurity concentration at each region.
In some cases, to compensate for lower impurity concentrations at a surface of an active region as a result of, e.g., high temperatures and/or etching solutions used to form an insulation layer and/or a trench region defining the active region, a higher dose of impurity has been supplied. However, when a channel impurity layer is formed by increasing a dose of impurity, gate induced drain leakage (GIDL) may occur around, e.g., a selection transistor of a NAND-type flash memory device, and may thereby deteriorate boosting efficiency.